Ramesh Narayanaswamy

~Ramesh_Narayanaswamy1

1

论文总数

1.0

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7.3

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NeurIPS

1

发表论文 (1 篇)

20251 篇

VeriLoC: Line-of-Code Level Prediction of Hardware Design Quality from Verilog Code

NeurIPS 2025Poster

合作者 (7)

Andre Nakkab1 篇

Badri P Gopalan1 篇

Jitendra Bhandari1 篇

Johann Knechtel1 篇

Raghu Vamshi Hemadri1 篇

Ramesh Karri1 篇

Siddharth Garg1 篇