AnalogGenie-Lite: Enhancing Scalability and Precision in Circuit Topology Discovery through Lightweight Graph Modeling

We appreciate the reviewer's valuable comments.

Q1: It would be better if there is a discussion for time cost of each method. The two techniques introduced in this work, subgraph mining and solving Chinese Postman problem, seems to introduce much time.

We would like to evaluate the time cost of our subgraph mining algorithm and Algorithm 1 for solving the Chinese postman problem empirically. Our experiment is conducted on a PC with a 16‐core i9-12900KF CPU and 32 GB RAM. We run each algorithm 5 times on the analog circuit dataset. The mean runtime for the subgraph mining algorithm is 1473.74 seconds, and Algorithm 1 is 783.30 seconds. This one-time preprocessing cost can be amortized by the substantial memory and time savings during model pre-training.

Q2: From the formulation of the task, it is possible to leverage pre-trained language model, e.g., old models such as T5 or new models such as Llama and GPT-4o, as a prior and conduct fine-tuning on it. It would be better if there are discussion about them and a comparison with current train-from-scratch approach.

We appreciate the reviewer’s suggestion. In our study, we have already compared our train-from-scratch approach with methods that leverage pre-trained language models. Specifically, our experiments included:

• AnalogCoder [1]: a GPT-4o-based model using domain-specific prompt engineering.
• LaMAGIC [2]: a model fine-tuned on a FLAN-T5-base backbone.
• Artisan [3]: a model fine-tuned on a Llama2-7b backbone.

As detailed in Table 1 of our paper, our approach outperforms these baselines across several key metrics, including validity, scalability, versatility, novelty, and FoM.

Q3: the generation task in this work seems to mean unconditional generation, where we cannot control what will be generated. Is that right? Can it be used for text-based generation, where text describes the design requirements.

Our approach is not limited to unconditional generation. We incorporate mechanisms to steer the generation process toward a specific type of analog circuit topologies optimized for key performance metrics (e.g., Figure of Merit) by leveraging reinforcement learning with human feedback (RLHF) to fine-tune our pre-trained model. The process begins with training a reward model that evaluates generated topologies based on validity, circuit type, and performance using a dataset labeled by humans. Once this reward model is trained, we apply proximal policy optimization (PPO) [4] to iteratively refine the pre-trained model. In each training epoch, the model generates a batch of candidate topologies that are scored by the reward model, and the model parameters are adjusted to maximize the expected accumulated reward scores, effectively steering the generation toward high-performance designs. Although AnalogGenie-Lite currently does not support text-based input, its underlying next-token-prediction mechanism makes it naturally compatible with text generation, and by augmenting the netlist dataset with text-based descriptions of design requirements, we can extend our approach to include text-based control in future iterations (as acknowledged by the reviewer in Relation To Broader Scientific Literature section).

[1] Lai, Yao, et al. "Analogcoder: Analog circuit design via training-free code generation." arXiv preprint arXiv:2405.14918 (2024).

[2] Chang, Chen-Chia, et al. "Lamagic: Language-model-based topology generation for analog integrated circuits." arXiv preprint arXiv:2407.18269 (2024).

[3] Chen, Zihao, et al. "Artisan: Automated operational amplifier design via domain-specific large language model." Proceedings of the 61st ACM/IEEE Design Automation Conference. 2024.

[4] Ouyang, Long, et al. "Training language models to follow instructions with human feedback." Advances in neural information processing systems 35 (2022): 27730-27744.

Thanks for the reviewer's valuable and constructive feedback.

W1 & Q1: Ablation: Additional discussion on the sensitivity of performance to hyperparameter choices in the pruning and subgraph mining processes could be beneficial. How sensitive is the overall performance to the threshold used for pruning isolated nodes in subgraph modeling?

We conducted an ablation study to assess how AnalogGenie-Lite's performance responds to two key hyperparameters in our subgraph pruning process: (1) the frequency threshold of subgraph occurrence in the dataset and (2) the threshold for the number of isolated nodes in a subgraph. Specifically, we experimented with frequency thresholds of 5%, 25%, and 50% along with isolated node thresholds of 4 and 8. A subgraph is pruned if its occurrence frequency exceeds the chosen threshold and if it contains more isolated nodes than the specified limit. After compressing the dataset, we followed our standard pretraining and finetuning procedure for AnalogGenie-Lite. The results are summarized in the table below:

Overall, most performance metrics are relatively insensitive to these hyperparameters. The one exception is scalability, which is notably affected by changes in the thresholds due to their direct impact on the number of subgraph pruning candidates. Notably, in 5% frequency results, aggressively lowering the thresholds to achieve higher compression introduces a large number of infrequently used special tokens into the tokenizer, which adversely affects training and ultimately hurts performance on metrics other than scalability.

C1 & Q2: More detailed analysis regarding the integration of reinforcement learning with human feedback—specifically, how this impacts circuit FoM—could further enhance the paper. Could you elaborate on how reinforcement learning with human feedback is integrated into the generation process, in detail?

AnalogGenie-Lite pretrained-only model can initially produce a wide variety of analog circuit topologies without inherent bias toward specific performance metrics. To optimize it for generating high-performance circuits, we integrate RLHF in a two-step fine-tuning process. First, a reward model—trained on human-labeled examples—is used to score generated circuit topologies based on type and performance. Then, we fine-tune the pretrained model with PPO: the model generates new designs, the reward model assigns scores, and PPO updates the model to maximize the expected accumulated reward. This process directs the pretrained model toward optimal circuits, boosting the FoM for Op-Amps from 291.3 to 15017.7 and for power converters from 2.6 to 4.02.

Q3: How does AnalogGenie-Lite handle circuits with highly irregular or non-repetitive topologies that may not benefit from subgraph simplification?

Our approach is robust even for highly irregular circuit topologies that do not benefit from subgraph simplification. Specifically, we exploit a common feature in all analog circuits: the ground node, which connects to multiple device pins within the circuit. By consolidating these multi-pin shared edge connections through graph-level simplification, AnalogGenie-Lite can maintain compression rate without subgraph simplification. As shown in Figure 5, our graph-level method delivers a mean compression rate of 40.28$\times$ compared to adjacency matrix representation without the subgraph simplification. Furthermore, because analog circuit graphs are inherently sparse, our optimal sequence modeling strategy can maintain an additional 1.43$\times$ improvement in compression performance. These two approaches ensure that our method remains effective even when subgraph simplification is less applicable.

Thanks for the constructive comments. We address your concerns below.

Q1: Why the baseline, AnalogGenie, is the version without fine-tuning? This work also does fine-tuning by reinforcement learning with human feedback. It seems that there is an unfair comparison.

Our evaluation is designed to ensure fairness between our work and the baseline AnalogGenie. As discussed in Section 4.1 on the training setup, our work is not fine-tuned for evaluations of validity, scalability, versatility, and novelty. We apply RLHF only when evaluating its performance on a specific circuit type, thereby optimizing it for high-performance circuits. This approach allows us to assess our work both as a versatile foundation model and as a specialized agent. For our baseline, AnalogGenie is evaluated under the same conditions—it is pre-trained solely for assessing validity, scalability, versatility, and novelty. For performance evaluation, AnalogGenie is also fine-tuned with RLHF.

Q2: While the authors compress the graph to sequence, which reduce the complexity of the problem to linear, it should also be important analyze the computational complexity of the 'Chinese postman problem'.

We would like to empirically evaluate the computational cost of Algorithm 1 for solving the Chinese postman problem. Our experiments on a 16‐core i9-12900KF (32 GB RAM) show that Algorithm 1 takes, on average, 937.36 seconds for the Protein dataset while the Analog circuit and Ego datasets took 783.30 and 296.06 seconds, respectively. This one-time preprocessing cost is justified by the substantial memory savings during training.

Q3: Could the authors also discuss other algorithms converting graph to sequence? I am just curious why the authors choose this method to compress the graph.

Prior method like adjacency vector encodes each node by its connections to all preceding nodes, which results in a $O\left(n^2\right)$ complexity ($n$ is the number of nodes and $m$ is the number of edges). Alternatives include a recursive binary tree [3] that conditions on matrix rows and columns, reducing complexity to $O((n+m) \log n)$, and a graph token sequence[4] that first encodes node definitions followed by edge, achieving $O(n+m)$. We choose the Chinese postman sequence for two reasons. First, it has a complexity of $O\left(m\right)$, which is efficient for representing sparse graphs like analog circuits. Second, representing the graph as a traversal path not only preserves critical structure information but also aligns well with the behavior of language models by predicting the next token based on the current context.

Q4: Graphs can also be compressed by other algorithms, the simplest one is just record the edges and their corresponding nodes. However, the authors only compare it with vanilla adjacency matrix and sounds like overclaim their scalability (compression rate).

We appreciate the reviewer's suggestion. While an edge list is compact, prior work LaMAGIC has already explored this approach by representing graphs as a list of hyperedges. In that work, the edge-list underperformed compared to the adjacency matrix. This indicates that, despite its compactness, the oversimplified structure of an edge list makes it harder for language models to learn and generate complex graph patterns. In contrast, our method is designed to not only compress the graph but also to preserve structural information critical for effective generation. Moreover, our experiments are not limited to comparisons with the adjacency matrix. We also compare our work with the AnalogGenie sequence in Figure 5 and the adjacency vector in Figure 6. In response to the reviewer's valuable suggestion, we will extend our case study in Q5 to include additional graph compression algorithms.

Q5: Why only the authors only conduct case study for protein and ego graphs? While discovering circuit topologies is an interesting problem, I think the contribution will be greatly improved if the proposed methods can be applied to more fields.

We have expanded our case study to include molecules [1] and 3D point cloud graphs [2]. As shown below, our method consistently outperforms alternatives in compression rate relative to the adjacency matrix.

[1] Ramakrishnan, et al. "Quantum chemistry structures and properties of 134 kilo molecules." Scientific data, 2014.

[2] Neumann, et al. "Graph kernels for object category prediction in task-dependent robot grasping." MLG. 2013.

[3] Dai, et al. "Scalable deep generative modeling for sparse graphs." ICML, 2020.

[4] Chen, et al. "Graph Generative Pre-trained Transformer." arXiv, 2025.

Q1: Compared to the original AnalogGenie work, the innovation appears incremental. Although the improved scalability is promising, the performance gains also seem relatively modest in scope.

We appreciate the reviewer’s insightful comments and would like to elaborate on our innovations in this paper. Our approach is novel on three levels—graph, subgraph, and sequence—and each contributes significantly to improving circuit generation quality in terms of validity, scalability, and performance.

At the graph level, we introduce a new graph representation that is considerably simpler than the current SOTA device-pin graph representation [1]. Specifically, for multi-pin shared edge connections, our method achieves a space complexity of $O\left(n\right)$, compared to the $O\left(n^2\right)$ required by existing approaches. This advancement results in a 6.6% improvement in generation validity, a scalability boost of 2.9$\times$, and a performance (FoM) increase of 982.5 compared to the current SOTA [1].

At the subgraph level, we are the first, to our knowledge, to apply frequent subgraph mining techniques to an analog circuit database to identify frequently reused subcircuits and replace them with compact representations. This novel contribution leads to an additional 7.2% improvement in generation validity, enhances scalability by 1.24$\times$, and increases performance (FoM) by 40.2 on top of the improvements achieved at the graph level.

At the sequence level, we model a circuit graph as an optimal sequence by formulating it as the shortest closed path that visits every edge of an undirected graph at least once, effectively solving the Chinese Postman Problem [2]. This approach significantly reduces sequence length and further improves generation validity by 9.7%, scalability by 1.43$\times$, and performance (FoM) by 250.2 relative to the subgraph-level method.

Finally, we clarify that our method's performance improvements are significant by comparing it to the historical development of electronic design automation algorithms for analog circuits' topology discovery. For instance, while op-amp circuits have been extensively studied by existing EDA algorithms [3-6], early works such as Artisan [3] achieved an 1847.7 FoM gain using LLM-based op-amp synthesis over traditional reinforcement learning methods [4]. On top of that, the current SOTA [1] further secures an additional 975.3 FoM gain relative to Artisan. By integrating our three innovative techniques mentioned earlier, AnalogGenie-Lite attains an overall improvement of 23.5% in generation validity, a scalability enhancement of 5.14$\times$, and a FoM gain of 1272.9 compared to the current SOTA [1]. These results underscore the substantial advancement our approach offers in tackling the challenging domain of analog circuit design, pushing the circuit performance's limit in the post–Moore's law era.

[1] Gao, Jian, et al. "AnalogGenie: A Generative Engine for Automatic Discovery of Analog Circuit Topologies." arXiv preprint arXiv:2503.00205 (2025).

[2] Edmonds, Jack, and Ellis L. Johnson. "Matching, Euler tours and the Chinese postman." Mathematical programming 5 (1973): 88-124.

[3] Chen, Zihao, et al. "Artisan: Automated operational amplifier design via domain-specific large language model." Proceedings of the 61st ACM/IEEE Design Automation Conference. 2024.

[4] Chen, Zihao, et al. "Total: Topology optimization of operational amplifier via reinforcement learning." 2023 24th International Symposium on Quality Electronic Design (ISQED). IEEE, 2023.

[5] Lu, Jialin, et al. "Topology optimization of operational amplifier in continuous space via graph embedding." 2022 Design, Automation & Test in Europe Conference & Exhibition (DATE). IEEE, 2022.

[6] Zhao, Zhenxin, and Lihong Zhang. "An automated topology synthesis framework for analog integrated circuits." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 39.12 (2020): 4325-4337.