AUTOCIRCUIT-RL: Reinforcement Learning-Driven LLM for Automated Circuit Topology Generation

We appreciate the reviewer’s detailed feedback and address the concerns as follows:

Scalability Concerns:

Our experiments primarily focus on 4–5 component circuits, with a few-shot evaluation for 6–10 component designs using only 1,000 training samples. Although success rates drop for larger circuits due to increased complexity, this decline is an inherent challenge of scaling circuit design—not a fundamental limitation of our method. Notably, even for larger circuits, our model achieves over 60% success in generating valid designs. Moreover, our experiments show that employing a multi-sample generation strategy (quantified by our SuccessRate@m metric) substantially improves performance. For instance, using m=3 or m=5 yields average generation times of 5.1 and 8.5 seconds, respectively, while markedly increasing the probability of finding a valid design. This approach effectively mitigates performance drops without necessitating massive additional training data. We are actively exploring enhanced RL sampling techniques and efficient data augmentation strategies to further improve scalability.

Comparison with Other Baselines:

We appreciate the reviewer’s suggestion to compare our approach with recent methods such as AnalogCoder and Artisan. While both methods provide valuable contributions to LLM-based circuit synthesis, our work differs fundamentally in methodology and scope:

AnalogCoder relies on training-free prompt engineering to generate SPICE netlists, but it lacks an adaptive optimization mechanism, making it less suitable for synthesizing novel or complex topologies. Moreover, it does not cover power converters that require specialized design constraints, i.e., efficiency, and output voltage.

Artisan is specialized for operational amplifier design using domain-specific LLMs, whereas our approach is focused on power convertors, though they could be more generalizable across different analog topologies.

Our method (AutoCircuit-RL) introduces a two-phase process:

a. Instruction-tuned LLM generates diverse circuit topologies.

b. Reinforcement learning (RL) refinement optimizes the topologies for multiple objectives (validity, efficiency, and output voltage) through reward-driven feedback.

This novel dual-phase strategy allows us to tackle multi-objective design challenges in power convertors more effectively. Additionally, we plan to add more quantitative comparisons with additional baselines, to demonstrate that our approach achieves superior design quality and efficiency. We will include these updated results in the final version if this is accepted.

Reference Clarifications:

Thank you for pointing this out. We acknowledge the issue of duplicate references and will correct them in the final manuscript. We will also include additional relevant references (e.g., Atelier, AnalogXpert) to better situate our work within the broader literature.

Thank you for your thoughtful review.

Device Sizing and Evaluation Metrics:

Our approach primarily focuses on generating circuit topologies, which includes selecting the devices and their interconnections. The device parameters (e.g., capacitor, inductor, and MOSFET sizes) are set based on standard design guidelines commonly used in power electronics (e.g., 10μF for capacitors, 10μH for inductors, and fixed MOSFET parameters). This decision allows us to isolate and optimize the topology generation task while maintaining consistency in evaluations. We plan to focus on optimizing device parameters in the future. The metrics reported in Section 4.2—including circuit validity, efficiency, and output voltage—are computed using these standardized component values. While our method does not dynamically generate device sizes, the reported metrics remain valid and meaningful as they reflect the performance of different topologies under fixed design constraints.

Comparison with AnalogCoder and LaMAGIC:

While both AnalogCoder and LaMAGIC use LLMs for circuit synthesis, our approach differs in its methodology and optimization strategy:

AutoCircuit-RL (Ours):

We employ a two-phase process: (i) an LLM first generates initial circuit topologies through instruction tuning, and (ii) a reinforcement learning (RL) refinement phase iteratively optimizes these topologies using reward models that account for circuit validity, efficiency, and output voltage. This allows us to explore a much wider design space and generate more robust and scalable topologies, even with limited training data. Our empirical results show a 12–14% increase in circuit validity and a 14–16% improvement in efficiency, demonstrating the effectiveness of our RL-based refinement.

AnalogCoder:

This approach uses domain-specific prompt engineering to generate PySpice code for standard analog circuits. However, it relies on a predefined synthesis library, which limits its ability to explore novel or complex topologies. Moreover, it does not cover power converters that require specialized design constraints, i.e., efficiency, and output voltage.

LaMAGIC:

Similar to other LLM-based methods, LaMAGIC generates circuits using supervised fine-tuning with pre-trained models but does not incorporate reinforcement learning. As a result, it lacks an iterative refinement process that can optimize designs beyond their initial generation. Our reward-driven optimization provides a key advantage in enhancing both circuit validity and efficiency.

Thank you for your valuable feedback.

Benchmarking Datasets:

To the best knowledge of the authors, currently in the domain of analog circuit topology generation, there is no standard benchmarking datasets. All the recent publications in this domain would spend considerable effort in curating initial dataset. Our focus is on power converter synthesis—a domain with unique design constraints such as efficiency, output voltage, and component pool. We have domain experts in power converter design who helped us examine the evaluation setup and validity of the dataset. Our dataset is specifically curated to represent these constraints and ensure that our evaluation reflects real-world challenges in analog circuit design. This specialized dataset is critical for assessing generative performance in our targeted application area.

Evaluation of Key Metrics:

Our study comprehensively evaluates correctness, efficiency, and scalability by comparing multiple LLM-based approaches with a non-LLM baseline (GraphVAE) and by contrasting zero-shot, in-context learning, and fine-tuning methods. These layered evaluations clearly demonstrate that our framework not only generates more valid circuits but also achieves significant improvements in efficiency and scalability.

Runtime Complexity Analysis:

Our method generates a new design in approximately 1.7 seconds using 2 NVIDIA V100 GPUs, which is a significant improvement over traditional search-based methods that typically require hundreds of seconds due to large number of simulation queries. This efficiency underscores the practical advantages of our RL-based refinement approach. We acknowledge that further runtime complexity analysis against standardized datasets could provide additional insights and plan to include such analyses in our final manuscript upon acceptance.

We appreciate the reviewer’s constructive feedback and address each concern below.

Comparison with Auto-SPICE [1]:

Our work fundamentally differs from Auto-SPICE, which focuses on generating SPICE netlists via domain-specific prompt engineering for dataset creation. It aims to generate large-scale SPICE netlist datasets from analog textbooks by annotating netlist schematics. In contrast, our approach—AutoCircuit-RL—goes beyond merely creating a dataset. It employs a two-phase process: first, an instruction-tuned LLM generates initial circuit topologies; then, a reinforcement learning (RL) refinement phase iteratively optimizes these topologies for multiple objectives (validity, efficiency, and expected output voltage). This reward-driven optimization enables our method to produce more robust designs and scale to more complex circuits.

Our work differs from Auto-SPICE in several key aspects. Auto-SPICE focuses on automating the creation of large-scale SPICE netlist datasets (e.g., Masala-CHAI) by extracting netlists from schematic images and their captions, and then uses these datasets to fine-tune LLMs for SPICE netlist generation. In contrast, our approach—AutoCircuit-RL—is centered on the methodology of generating circuit topologies that adhere to specific design constraints using a synthetic dataset. We first leverage instruction tuning to generate initial topologies based on various user prompts, and then apply reinforcement learning to iteratively refine these designs with respect to objectives such as circuit validity, efficiency, and output voltage.

While our methodology could potentially benefit from integrating datasets like those produced by Auto-SPICE, doing so addresses a different problem: dataset creation versus constrained topology synthesis. Our work tackles the challenge of generating circuit topologies under diverse, constraint-specific scenarios—a distinct and complementary problem to that addressed by Auto-SPICE.

Dataset Details:

We plan to release the code and dataset upon acceptance to support reproducibility. We have provided details of dataset collection in Section 2. Each data sample will include a circuit netlist representing the topology, along with its corresponding duty cycle, output voltage and efficiency obtained from the simulator.In the paper, “unique netlists” refer to differences in connectivity and node indexing, while “unique designs” abstract away superficial ordering variations. We will provide a representative sample subset for illustration.

Suggestions:

Qualitative Examples and Evaluation:

Thank you for the suggestion. We have included qualitative examples in the Appendix that showcase generated circuit topologies and highlight successful cases. These examples illustrate how our model adapts to design constraints and generates diverse solutions. We plan to expand these qualitative evaluations further in the final version.

Questions:

Computation Cost:

Our method generates a circuit design in approximately 1.7 seconds using 2 NVIDIA V100 GPUs—substantially faster than traditional search-based methods, which often require hundreds of seconds due to extensive SPICE simulations. This efficiency is a direct result of our two-phase, reward-driven RL refinement process.

Comparison with Other Baselines:

We appreciate the suggestion to compare our approach with recent methods such as AnalogCoder and Artisan. While our primary comparisons have been with GraphVAE and other LLM-based methods, additional analyses show that our RL refinement significantly improves circuit validity and efficiency compared to these approaches. AnalogCoder relies on training-free code generation, which limits its ability to explore novel or complex topologies, whereas our method’s iterative refinement better addresses the multi-objective challenges of power converter design. AnalogCoder generates amplifier circuits while this work generates power converter topologies, it’s not a direct comparison.

Failure Cases and Detailed Prompts:

We recognize that including failure cases and error analysis will provide a clearer understanding of our approach and highlight potential areas for future improvement. While Table 3 currently presents examples of successful generation scenarios, we will expand it to include failure cases as well. Additionally, Table 3 in the Appendix provides detailed prompts for different constraint-related scenarios, offering insights into the model’s behavior under various conditions. These analyses help diagnose existing limitations and inform future refinements. We will incorporate further discussion on these aspects in the final manuscript upon acceptance.

Learning Curve of RL Tuning:

The convergence curve of RL tuning will be added in the supplementary section upon acceptance.

Code Implementation:

We will opensource the code if this manuscript is accepted.