MIHC: Multi-View Interpretable Hypergraph Neural Networks with Information Bottleneck for Chip Congestion Prediction

We sincerely thank the reviewer for taking the time to review our paper and for recognizing our contributions, including the clear comparative analysis of related work, the significance of chip congestion prediction, the intuitive design of the interpretable subgraph module, the comprehensive and strong experimental results, and the practical runtime and memory analysis. In the following, we provide thoughtful and thorough responses to all of the reviewer’s questions.

W1: Could you please detail the runtime comparison with other baseline methods?

A: Thank you for the helpful question regarding runtime comparison. To provide a clear and fair evaluation, we selected the best-performing baseline methods from cell-based (DE-HNN) and grid-based (Lay-Net) approaches for runtime comparison on the same NVIDIA A100 80GB GPU setup:

From a comprehensive performance-runtime perspective, our MIHC achieves the best trade-off: it maintains competitive inference speed comparable to DE-HNN while delivering significantly superior prediction accuracy (16.67% NMAE reduction on ISPD2015-F) and providing interpretability capabilities that neither baseline offers. Compared to Lay-Net, our method achieves both better runtime efficiency and higher accuracy, making it more suitable for practical industrial applications.

Q1: Is there any chance that your method could provide a method for chip congestion optimization? Like congestion-driven placement?

A: Thank you for the insightful question. While our current work focuses on congestion prediction, we believe that the architecture of MIHC is well suited to support congestion-aware design optimization tasks. In particular, MIHC’s ability to identify congestion-critical regions and jointly reason over netlist and layout information makes it a promising candidate for both chip-level optimization and placement refinement.

Chip Congestion Optimization: Our Information Bottleneck mechanism identifies critical congestion-correlated regions (as shown in Figure 2), revealing not just where congestion occurs but which local structures cause these anomalies. The bottleneck subgraphs identified by our method could guide chip optimization by highlighting problematic regions that need cell redistribution or routing resource allocation. The interpretable nature of our predictions provides actionable guidance for designers to make targeted optimizations rather than generic congestion mitigation, enabling more efficient use of routing resources and improved overall chip performance.

Congestion-Driven Placement: For placement-specific applications, our method could be integrated into placement algorithms to evaluate congestion impact during cell positioning. By simultaneously processing both netlist topology and layout geometry, our method can provide insights into how placement decisions affect congestion from both connectivity and spatial perspectives. This multi-view analysis capability allows placement tools to consider both topological connectivity constraints and geometric layout effects simultaneously, leading to more informed placement decisions that proactively avoid congestion hotspots rather than reactively addressing them post-placement.

Dear Reviewer ERG1,

Please join the discussion to assess whether the authors’ response has adequately addressed your question. Thank you very much for your engagement!

Best regards, AC

We sincerely appreciate the reviewer for the positive feedback, especially on the effectiveness of MIHC’s fusion strategy and its strong performance on ISPD2015-B and CircuitNet-N28. We now provide detailed, point-by-point responses to the reviewer’s comments as follows.

W1: The illustration of MIHC’s interpretability performance(RQ2) is not clear.

A1: Thank you for your valuable feedback. We recognize that the interpretability evaluation of MIHC (RQ2) can benefit from a clearer explanation. To address this, we demonstrate MIHC's interpretability performance through two complementary tasks: chip congestion prediction and the MNIST 0/1 classification benchmark.

In the chip congestion prediction scenario (Figure 2 in the main paper), MIHC is evaluated on its ability to detect meaningful structural patterns that contribute to congestion. As illustrated in the heatmaps, the bottleneck subgraphs extracted by our model effectively capture critical regions where congestion occurs. These regions align closely with the ground truth patterns, confirming that MIHC not only detects individual anomalies but also identifies the local substructures responsible for those anomalies. This is especially important in circuit design, where congestion often arises from interactions among components rather than from isolated nodes. Our information bottleneck mechanism highlights these structurally significant areas, offering insights beyond what node-level detection alone can provide.

To further support the interpretability of MIHC, we also include an evaluation on the MNIST 0/1 dataset (Table 15 in the Appendix). This dataset is commonly used in interpretability studies because it contains semantically meaningful explainable labels. Since interpretability benchmarks are lacking in the chip congestion domain, we use MNIST as a well-established complement. The results show that MIHC achieves consistently high scores across a range of evaluation metrics, demonstrating robustness and generalizability. The performance indicates that our method provides coherent and faithful explanations across different data types. Compared to baseline models, MIHC exhibits a better balance between precision and recall. For example, GAT+GNNE achieves high recall but low precision, producing noisy explanations, while SIGNET prioritizes precision but overlooks broader node relationships, resulting in poor recall. MIHC, by contrast, maintains both high fidelity and meaningful structural coverage.

Overall, the core interpretability mechanism of MIHC—extracting the most informative subgraph responsible for predictions—remains consistent across both chip and MNIST scenarios. This unified explanation framework ensures that the insights generated are not only accurate but also actionable, making the model's decisions more transparent and trustworthy for real-world applications.

Q1: In equation (9), $h_e^C$ and $h_e^G$ are concatenated. Does this mean cell-based and grid-based hypergraphs share the same topological structure (Because equation (9) concatenates the embedding of the same edge from two hypergraphs)? If not, how do you construct cell-based and grid-based hypergraphs to achieve this?

A: Thank you for this important clarification question. The cell-based and grid-based hypergraphs do not share the same topological structure, as they operate on different node types (cells vs. grid regions). However, they share corresponding hyperedges that represent the same nets, which enables meaningful concatenation in Equation (9).

Different Topologies, Same Net Correspondence: While the two hypergraphs have different topological structures due to different node representations, their hyperedges correspond to identical nets in the circuit. This net-based correspondence is the key to our multi-view information fusion approach—we use net hyperedges as bridges to enable information exchange between the two hypergraph representations.

Construction Example: As illustrated in Figure 1(c), consider the purple hyperedge 1: in the cell-based hypergraph, it connects blue cells 2, 5, 6, and 7 that are connected by the same net; in the grid-based hypergraph, it connects green grid cells 1, 4, 5, and 6 that are traversed by the same net. Although the connected nodes differ, both hyperedges represent the same physical net, making their embeddings ($h_e^C$ and $h_e^G$) complementary views of the same connectivity information.

This net-based bridging mechanism allows us to meaningfully concatenate embeddings from structurally different hypergraphs while preserving the semantic correspondence between views.

Dear Reviewer 8ndm,

Please join the discussion to assess whether the authors’ response has adequately addressed your questions and concerns. Thank you very much for your engagement!

Best regards, AC

Dear Reviewer 8ndm,

Thank you for your thorough review and positive feedback on our paper about MIHC for chip congestion prediction. We deeply appreciate your recognition of our framework's effectiveness in fusing cell-based and grid-based information and the strong performance results on ISPD2015-B and CircuitNet-N28.

We have addressed your concerns regarding MIHC's interpretability performance illustration, the topological structure relationship between cell-based and grid-based hypergraphs, and the concatenation mechanism in equation (9) in our detailed rebuttal. We particularly provided comprehensive explanations of how our net-based correspondence enables meaningful multi-view fusion despite different topological structures, along with additional MNIST evaluation results to demonstrate the robustness of our interpretability mechanism across different domains.

We would be extremely grateful if you could share your thoughts on our response and let us know if our clarification of the hypergraph construction methodology and interpretability evaluation have adequately addressed your questions, or if there are any further concerns we could clarify.

Thank you again for your time and consideration.

Best regards,

All the Authors

We thank the reviewer for carefully identifying the concern regarding generalization and training cost, which we address in detail below, point by point. We also appreciate the positive remarks on our empirical results, overall design, and writing clarity.

W1: The biggest weakness in my mind has to do with generalization. I wasn't clear whether the paper trains a single model and tries to generalize across all designs, or whether there were separate models trained for different designs.

A: Thank you for bringing this concern about model generalization. To clarify, in this work, we train a single model for each dataset that generalizes across all designs within that dataset. Specifically, we obtain three models in total: one trained on ISPD2015-B, one on ISPD2015-F, and one on CircuitNet-N28. Each model is trained to handle multiple different circuit designs simultaneously. For example, ISPD2015-F contains 20 different industrial designs (as shown in Table 6), and our model learns to predict congestion across all these diverse designs with a single set of parameters.

W2 + Q1: I had questions about the training/test split from the datasets the authors created, because generally it's easier for a model to make predictions about a design if very closely related circuits are in the training set. And in this case it appears the authors split up designs so that pieces of each design were both in the training set and the test set.

A: Thank you for raising this important and constructive question about our experimental setup. In our original experiments, we followed a placement-level split similar to Exp1 in Lay-Net [1], where different placement solutions from the same design appeared in both training and test sets. While this approach is useful for evaluating model performance on known design types, we notice that it could bring concerns about generalization capability since models might learn design-specific patterns rather than generalizable congestion prediction principles.

To address your concern and provide a more rigorous evaluation of generalization capability, we have conducted additional experiments following the unseen design experimental setup (Exp2) from Lay-Net [1]. In this setting, we performed design-level splits where training and test sets contain completely different circuit designs, ensuring no overlap between design families. Due to the time limit, we focus on ISPD2015-B and ISPD2015-F datasets for these additional generalization experiments. For ISPD2015-B, we divided the 15 designs into Group A (8 designs: des_perf series, fft series, and edit_dist_a) and Group B (7 designs: matrix_mult series and pci_bridge32 series). For ISPD2015-F, we used a 10 vs 10 split, with Group A containing des_perf series, fft series, edit_dist_a, superblue12, and superblue16_a, while Group B included matrix_mult series, pci_bridge32 series, superblue11_a, superblue14, and superblue19. This partitioning ensures that designs with the same prefix remain together, preventing any potential issues between functionally similar circuits. Following the Lay-Net [1] Exp2 experimental setup, we conducted bidirectional evaluation by training on Group A and testing on Group B, then reversing the roles to train on Group B and test on Group A.

The results from our unseen design experiments demonstrate significantly more challenging conditions, with substantial performance degradation across all methods compared to the seen design setting. As shown in the following experimental tables, which present the comprehensive results for both A→B and B→A training-testing directions across ISPD2015-B and ISPD2015-F datasets, MIHC maintains superior performance over state-of-the-art baselines in the vast majority of evaluation metrics across both cell-based and grid-based prediction tasks. For instance, in the B→A experiments, MIHC achieves the best performance in 18 out of 20 metrics, with only occasional slight disadvantages in specific cases such as Lay-Net's marginally better performance in grid-based Spearman correlation on ISPD2015-F. These results provide evidence that our method achieves genuine generalization capability rather than simply memorizing design-specific characteristics, offering a more realistic and stringent evaluation that better reflects real-world scenarios where models must generalize to entirely new circuit designs during practical deployment.

Table 1: Unseen Design Results - Group A Training → Group B Testing

Table 2: Unseen Design Results - Group B Training → Group A Testing

[1] Lay-Net: Grafting Netlist Knowledge on Layout-Based Congestion Prediction. TCAD 2025

W3: Additionally there are quite a few components to the model and it does seem a little complex. However, that is often the case in chip design methods. Finally I'd like to see more about training cost and frequency.

A: We acknowledge that MIHC involves multiple components, but each serves a specific purpose essential for balanced fusion of netlist and layout information and providing crucial interpretability for circuit design validation. As you noted, this complexity is typical in chip design methods given the inherent complexity of circuit data. As shown in Appendix C.8, our experiments on one NVIDIA A100 80GB GPU demonstrate practical performance: small circuits (~30K cells/nets) require ~0.9 seconds per training iteration and 3GB memory, while very large circuits (1.3M cells/nets) take ~5.0 seconds per training iteration and 22GB memory. Based on our experimental setup, the total training time is approximately 1.5 hours for ISPD2015-B, 2.8 hours for ISPD2015-F, and 15.6 hours for CircuitNet-N28. We will include this discussion in the revised version. These measurements confirm that despite the model's sophistication, its computational demands remain manageable for real-world industrial applications.

Q2: How often do you train a new model and how much compute does it take?

A: As shown in Appendix C.8, our experiments on one NVIDIA A100 80GB GPU demonstrate practical performance: small circuits (~30K cells/nets) require ~0.9 seconds per training iteration and 3GB memory, while very large circuits (1.3M cells/nets) take ~5.0 seconds per training iteration and 22GB memory. Based on our experimental setup, the total training time is approximately 1.5 hours for ISPD2015-B, 2.8 hours for ISPD2015-F, and 15.6 hours for CircuitNet-N28. These measurements confirm that despite the model's sophistication, its computational demands remain manageable for real-world industrial applications.

Dear Reviewer ibfY,

Please join the discussion to assess whether the authors’ response has adequately addressed your questions and concerns. Thank you very much for your engagement!

Best regards, AC

Dear Reviewer ibfY,

Thank you for your thorough review and constructive feedback on our paper about MIHC for congestion prediction in chip design. We deeply appreciate the time and effort you've dedicated to evaluating our work, particularly your insightful concerns about generalization and training costs.

We have addressed your questions regarding model generalization across different designs, the training/test split methodology, and computational requirements in our detailed rebuttal. We particularly provided comprehensive additional experiments with unseen design splits (following Lay-Net's Exp2 setup) to demonstrate genuine generalization capability, along with detailed training cost analysis showing practical computational requirements for real-world deployment.

We would be extremely grateful if you could share your thoughts on our response and let us know if our additional generalization experiments and training cost analysis have adequately addressed your concerns, or if there are any further questions we could clarify.

Thank you again for your time and consideration.

Best regards,

All the Authors