Bridging Layout and RTL: Knowledge Distillation based Timing Prediction

Dear Reviewer wjHP,

We sincerely appreciate the reviewer's positive remarks and valuable suggestions regarding our work, particularly concerning the sources of our benchmark data, the open-source plan, the fairness of comparisons with MasterRTL/RTL-Timer, and the discussion on comparison with other models. Below, we provide detailed answers to the points you raised.

1. Benchmark and Dataset Explanation

We have carefully chosen not to rely exclusively on certain existing publicly available datasets (e.g., ISCAS-89, ITC-99) because they are limited in size and diversity relative to our specific RTL-Layout prediction goals. For some large circuits, such as some large-scale CPUs or other designs, there may be many duplicate or essentially identical paths in the circuit, but the timing analysis is more associated with paths, which makes the distribution of the existing datasets not particularly satisfying; we wanted to minimize the occurrence of duplicate paths in the datasets and to make the dataset distribution as even and diverse as possible in order to allow more physical information to be learned by our model.

Instead, we collected more circuits of different types, functions, and sizes to reflect real-world industrial needs, including small arithmetic blocks, DSP modules, RISC-V subsystems, etc. This makes the prediction task harder, but we think it's more practical, pervasive, industrially valuable, and closer to the needs of actual industrial processes. These 2000+ designs come from GitHub, OpenCore, Hugging Face, and the open-source RISC-V project, ensuring broad functionality and design complexity coverage. The construction and cleaning of the dataset took us close to 5 months (see the reply to Reviewer DZ14 for more information on Layout data construction).

2. Open-Source Plan of Dataset and Codes

Furthermore, we have partially anonymized and released a subset of these designs and codes on public repositories (https://anonymous.4open.science/r/icml2025RTL-CBFD/); however, the size of back-end data and the space limitations on anonymous platforms prevent a complete release at this stage. We will expand our open dataset, aiming to foster community progress in AI4EDA.

We will keep enhancing our open-source repository (both the dataset and the code) to facilitate replication and iterative improvement by the community. Thanks to its graph-oriented modeling and distillation-based learning, we strongly believe our framework can be generalized to more designs.

3. Comparisons with MasterRTL and RTL-Timer

All results reported in the paper were derived by re-training and evaluating both MasterRTL [1] and RTL-Timer [2] on precisely the same dataset and evaluation protocols used by our method. Specifically:

1. Both are open-source implementations, and we reproduced them faithfully on our data, adhering to the authors' original procedures.
2. We used the same train/validation/test partitioning and ground-truth labels for all methods.
3. We evaluated using identical error metrics (MAPE, PCC, R²) for consistency.

4. Comparison with Other Models

We appreciate your recommendation to compare more thoroughly with related methods. Given that MasterRTL and RTL-Timer are among the most competitive open-source approaches for RTL-level timing prediction, demonstrating improvements over them provides a fair and substantial benchmark. According to prior works (e.g., [3], [4]), they didn't show the same performance as MasterRTL and RTL-Timer (e.g., > 10% gap in MAPE). We chose MasterRTL and RTL-Timer as the strongest public baselines.

Conclusion

Thanks again for the reviewer's supportive review and for highlighting the significance of benchmark diversity, fair comparisons, and open-source work. We will refine the discussion on data sources, continue expanding our dataset for broader coverage, and work to open-source the code with the full dataset. We hope the clarifications and updates will further underscore the practicality and robustness of our method.

We greatly value the reviewer's feedback and look forward to any additional suggestions. Looking forward to getting a higher rating from you!

References

[1] Fang, Wenji, et al. "Masterrtl: A pre-synthesis ppa estimation framework for any rtl design." 2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD). IEEE, 2023.

[2] Fang, Wenji, et al. "Annotating slack directly on your verilog: Fine-grained rtl timing evaluation for early optimization." Proceedings of the 61st ACM/IEEE Design Automation Conference. 2024.

[3] Xu, Ceyu, Chris Kjellqvist, and Lisa Wu Wills. "SNS's not a synthesizer: a deep-learning-based synthesis predictor." Proceedings of the 49th Annual International Symposium on Computer Architecture. 2022.

[4] Sengupta, Prianka, et al. "How good is your Verilog RTL code? A quick answer from machine learning." Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design. 2022.

                     PCC     R²      MAPE
Arrival Time (AT):   0.33   -0.76    83%
WNS:                 0.68    0.45    70%
TNS:                 0.41   -0.18    85%

                     PCC     R²      MAPE
Arrival Time (AT):   0.71    0.52    41%
WNS:                 0.73    0.68    53%
TNS:                 0.81    0.70    55%

Dear Reviewer 55gZ,

Thanks for your insightful comments. Your feedback greatly helped us refine our work. Below, we address your major concerns.

1. Efficiency vs. STA and Left-Shift

The entire flow from RTL to Layout to STA completion usually takes hours to days under rough quantitative estimation. Our method achieves several orders of magnitude faster runtime (see our response to Reviewer DZ14 for runtime details), with PCC 0.92, R² 0.85, and MAPE 16.87% for AT prediction—sufficient for early-stage RTL optimization [1], allowing the design flow to shift left.

2. Domain-specific Asynchronous Forward-Reverse Propagation

While bidirectional GNNs exist, we focus on an asynchronous forward-reverse approach tailored to timing semantics and physical contexts. This provides a deeper coupling between AI modeling and timing prediction domain-specific requirements:

• We incorporate multi-round, asynchronous updates to capture the long-range dependencies of registers, cells, and wires.
• This schema includes a form of "reverse constraint" flow, reflecting the physical insight that timing slack on downstream cells can impose constraints on upstream segments, especially under realistic RC conditions.
• Ablation results (Appendix) confirm simpler forward-only or fewer propagation rounds significantly degrade accuracy. This is caused by insufficient access to information about the surrounding circuit.

Our design goes beyond standard message passing to encode domain-specific timing semantics.

3. Multi-Granularity Distillation: Tailored to Circuit Structures

Our contribution lies in adapting multi-granularity distillation to EDA-specific adaptation:

• Tailoring to timing. Each granularity naturally corresponds to specific circuit structures relevant to timing: node-level for register endpoints, subgraph-level for critical local paths (fan-in/out cones), and global-level for capturing overall congestion (e.g., WNS/TNS).
• Simultaneous cross-stage distillation. By tuning the student at three granularities during distillation under the teacher, we alleviate the lack of physical cues at RTL by implicitly embedding critical layout-level physical information into the RTL GNN while focusing on the circuit's local and overall situation. As reviewer said, different distillation goals exhibit different behaviors because each of the three granularities plays a different role. As in Table 4, removing any one or two granularities reduces performance, confirming their complementary roles.

W/ Node performs well on AT's MAPE because it ignores the global or several paths in relation to each other and focuses only on registers. This leads to relatively good predictions in numerical values (MAPE) but weaker performance in correlation metrics (PCC, R²) than the full model, not giving the best results.

4. Teacher Model Limits and Distillation Balance

Our layout-level teacher is more accurate than the student but less precise than full STA due to the complexity of real RC extraction and GNN inherent limitations. The teacher’s precision naturally binds the student.

Regarding grid search of distillation-loss weights (α, β, γ), we observed small fluctuations across different metrics. We believe the optimal balance varies with data properties, circuit complexity, and task objective focus. Via coarse-grained grid search (lower computational overhead), we find equal weights (α = β = γ) that show superior multi-task average performance and make the ablation experiments clearer.

5. Distinction from Related Work

Compared to prior methods:

• [2] uses LLMs but lacks scalability and physical layout fidelity.
• [3] operates at layout stage, limiting early RTL optimization.
• [4] targets dynamic runtime behavior, not static timing.

Our method uniquely shifts accurate physical timing prediction to the RTL stage via cross-stage distillation.

6. Scalability to Industrial Designs

We are scaling to large designs (e.g., BOOM). While back-end optimization of million-gate designs is very demanding regarding runtime (more than days) and hardware resources, our graph-based architecture has shown scalability in principle, and we will endeavor to report results as large circuits are available.

Conclusion

Thanks for your constructive input, which helped us better articulate our approach's novelty and practical utility.

We appreciate your time and look forward to further suggestions. Hope to get a higher rating from you!

References

[1] Fang, Wenji, et al. "Annotating slack directly on your verilog: Fine-grained rtl timing evaluation for early optimization."

[2] Moravej, Reza, et al. "The Graph's Apprentice: Teaching an LLM Low Level Knowledge for Circuit Quality Estimation."

[3] Zhong, Ruizhe, et al. "Preroutgnn for timing prediction with order preserving partition: Global circuit pre-training, local delay learning and attentional cell modeling."

[4] DynamicRTL: RTL Representation Learning for Dynamic Circuit Behavior

Dear Reviewer DZ14,

Thank you for your constructive comments and recognition of our work's core contributions. We greatly appreciate your thoughtful feedback, which has helped us further refine and clarify several key aspects of our methodology. Below, we provide a structured response to your concerns.

1. Multiple EDA Back-end Parameters for Iterative Design Optimization

In constructing our dataset, we designed a unified, fully-automated back-end flow using state-of-the-art commercial tools—Synopsys Design Compiler and Cadence Innovus—with a consistent set of optimization switches (e.g., gate sizing, buffer insertion, cell movement, etc.). However, the circuits in our dataset were not finalized under a single fixed configuration.

For each design and each back-end optimization-related parameter (e.g., density thresholds, routing constraints, clock constraints), we automatically tried multiple sets of values and iteratively explored multiple different configurations, often conducting tens of design runs, until the circuit reached a state where:

• Placement density no longer increased, and
• Timing metrics converged stably through repeated optimization.

This convergence point is a practical proxy for physical design quality, reflecting an optimization level comparable to manually refined industrial flows. By doing so, we avoid biasing our dataset toward a singular "super-convergent" setting and instead generate diverse yet quality layouts more representative of industrial standards.

Importantly, this means our model is not tuned to predict timing under a specific tool configuration, but rather aims to approximate the best achievable timing performance after realistic optimization—an objective more aligned with industrial design goals.

2. Industrial Relevance and Methodological Scalability

We acknowledge that experienced experts in the industry may pursue further manual tuning to push timing closure closer to its theoretical optimum. However, given our goal of building a large RTL-to-Layout database covering many diverse designs, it is tough to explore every possible EDA configuration or foundry setting exhaustively.

While our approach may not guarantee absolute optimality for each circuit, it reflects a robust and converged implementation quality, providing a meaningful basis for our timing prediction framework. By generating datasets by "trying multiple parameters iterations until convergence", our multi-granularity cross-stage distillation framework maintains strong generality across various designs, process nodes, and EDA flows. The student model is designed to be easily extensible—new designs, tools, or manufacturing conditions can be seamlessly integrated. Rather than overfitting to a specific toolchain or configuration, our framework demonstrates that cross-stage learning is broadly applicable and practical. Once more finely tuned industrial data become available, our method can directly incorporate such data to enhance model accuracy further.

3. Runtime and Computational Efficiency

Performing the full RTL-to-Layout timing analysis flow—including synthesis, place-and-route, STA, etc.—typically consumes hours or even days for large circuits. In contrast, our GNN-based predictor operates at the RTL level, completing end-to-end inference in seconds to a few minutes for circuits ranging in size from thousands to millions of gates.

For example, on a 400K-gate CPU design running on an A100 GPU server:

• Logic synthesis takes ~30 minutes
• Backend optimization (e.g. place-and-route, etc.) takes over 6 hours
• STA requires ~33 minutes

By comparison:

• SOG extraction: ~65 seconds
• Final GNN inference: <100 seconds

This enables a speedup of over 10×, even against standalone STA, and far more when compared to the entire back-end flow. Moreover, our GNN model supports parallel processing, enabling efficient handling of large-scale circuits and making it viable for early design-stage performance estimation.

4. Data Availability and Reproducibility

To support reproducibility and peer evaluation, we have anonymized and released a subset of our code and data through an anonymous repository (https://anonymous.4open.science/r/icml2025RTL-CBFD/).

Due to the large file sizes and platform storage limitations, only a partial dataset is available at this stage (a clearer description of the data aspects is included in the reply to Reviewer wjHP; please check it out). We intend to release the full dataset and code upon paper acceptance, ensuring transparency and enabling broader research engagement.

Conclusion

Thanks for your thoughtful feedback. Your comments have helped us improve the clarity of our presentation, particularly around our data collection methodology, the generalizability of the proposed framework, and its practical runtime advantages.

We sincerely appreciate your review and very much hope to earn your affirmation and a higher rating!