GROOT: Graph Edge Re-growth and Partitioning for the Verification of Large Designs in Logic Synthesis

1. The related work section could be expanded for a more comprehensive comparison. The paper focuses primarily on comparing with GAMORA as the state-of-the-art, but there are numerous other GNNs in the EDA domain, such as HOGA [1] and DeepGate2 [2]. Additionally, the comparison only considers memory and runtime metrics with GAMORA, whereas it would be beneficial to also compare accuracy with other methods.
2. The paper lacks an ablation study, which is crucial for understanding the contribution of different components. Although the proposed method achieves 100% accuracy on 128-bit multipliers, there is no clear analysis regarding the performance improvement. An in-depth ablation study would help clarify these aspects.
3. The training process is not adequately explained. In Figure 2(c), the large graph is partitioned into sub-graphs, but in Figure 2(d), it appears that GraphSAGE is applied to the entire graph. Including more details about the training process would improve clarity, especially given the paper's emphasis on memory efficiency.

[1] Deng C, Yue Z, Yu C, et al. Less is More: Hop-Wise Graph Attention for Scalable and Generalizable Learning on Circuits. arXiv preprint arXiv:2403.01317, 2024. [2] Shi Z, Pan H, Khan S, et al. Deepgate2: Functionality-aware circuit representation learning. 2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD).

• Little information if any is provided behind the reasons of the proposed approach and how it is inspired or improves algorithmically over existing approaches.
• Ablation studies, analysis of the results and implications are incomplete or need a comprehensive restructuring.

-This authors argue that the proposed framework has domain specific knowledge included into the GNN optimization. However, the proposed circuit specific optimization including degree-based graph partitioning and node type classification are not new and they are already well studied in prior graph processing and GNN modeling. In addition, these optimizations are mostly specific to the graph structures and it is not quite relevant to the underlying EDA tasks. Although these approaches do enhance the GNN performance, it is also applicable to generic GNN tasks as long as the graph has varied vertex degree distribution, which is also quite common in social network-based graphs. Hence, the novelty of the proposed framework is limited.

-This work seems to mix various EDA tasks throughout this paper. For instance, the title indicates logic synthesis, The abstract talks about verification, Then, the experiments mentions multiplier accuracy. Although I know GNNs are intensively explored for circuit representation, I am still confused how GNNs are utilized in these different EDA tasks. More background knowledge is expected before going through the technical details especially for the AI-oriented conference.

-The experiments are all about multipliers. Although data width affects the structure of the circuits substantially, they still share many common blocks. Using small circuit blocks for training and testing on larger circuits with a large number of similar blocks are not quite convincing.

1. The reliance on partitioning and boundary edge re-growth introduces a trade-off between memory efficiency and accuracy. Specifically, as the number of partitions increases, accuracy tends to drop, particularly for complex graphs like Booth multipliers. This suggests that the edge re-growth algorithm may struggle to fully restore the lost connectivity and feature flow between partitions, which could lead to verification errors or degraded GNN performance in highly partitioned graphs.
2. GROOT’s custom kernel design is tailored for EDA graphs with extreme degree distributions (e.g., nodes with degrees above 512 or below 12). This specialization may reduce efficiency for graphs with less polarized or dynamically varying degree distributions. Additionally, the CUDA implementation with static workload partitioning and tree-based accumulation is optimized for certain degree profiles, which may not generalize well across diverse circuit designs or varying network topologies in EDA applications.
3. Despite achieving memory reduction via partitioning, the GPU memory requirements for larger circuits (e.g., 1024-bit multipliers) remain substantial. In some cases, even the highest-end NVIDIA A100 GPU (80 GB) approaches its capacity, especially when batch sizes are high. This indicates that GROOT might struggle to handle even larger or more complex circuits without requiring further optimizations or multi-GPU configurations, undermining the claim of single-GPU suitability
4. GROOT uses the GraphSAGE framework with a fixed set of node features based on the circuit's topology and polarity of input edges. This static approach may limit the adaptability of GROOT's GNN to dynamically changing circuits or circuits with less clear-cut node types (e.g., mixed or non-Boolean gate nodes). Such limitations could hinder GROOT's generalizability to new or unconventional circuit designs beyond those used in the study.
5. While the paper shows a qualitative trend of accuracy decline with increased partitioning, there’s limited quantitative analysis or formal model on how partition size or graph structure impacts accuracy and memory usage. This makes it challenging to predict how GROOT will perform on circuits with varying topologies, especially if accuracy requirements are stringent.