DeepLayout: Learning Neural Representations of Circuit Placement Layout

Q1 1.Ablation studies of ... is encouraged. 2.Ablation studies ... taken. A1 Ablation study of encoder modules Congestion prediction

Post-routing wire length prediction

Ablation study of pretrain loss: Congestion prediction

Post-routing wire length prediction

Q2 x∈W,y∈H ... format? A2 We will updating the notation to explicitly use range(W) and range(H).

Q3 For the pre-training task 1... K in line 266? A3 K denotes the total number of masked cells, where |Iₘ| = K (Algorithm 1, line 6).

Q4 If there is an one-to-one ... Eq. 3? A4 'min' indicates the optimization objective to minimize the loss. We will remove this notation from Eq 3 in our paper update.

Q5 For the pre-training task ... RPA? A5 As shown in Figure 5 (bottom left), RPA is computed for each net u covering area (xul,xuh,yul,yuh) using Eq 4 at every point (x,y) within this rectangle. The final layout RPA is obtained by aggregating values from all nets. We will enhance this explanation with additional visual aids in our final paper to improve clarity.

Q6 In my personal ... RPA. A6 Our explanation is divided into two parts to address your concerns.

1. RPA Feature Computation Without Masking: Initially, we compute the RPA feature without considering any masking. Utilizing Eq4 and 5, we perform a global routing probability overlay for all nets across the layout. This process generates a two-dimensional (2D) RPA feature map (w x H), which represents the global routing probability distribution across the entire layout. This feature map encapsulates the inherent routing characteristics of the layout, serving as a foundational element for subsequent processing.
2. Self-Supervised Masked Reconstruction: Our objective is to enable the network to reconstruct the routing probabilities of masked grid nodes to their original states before masking. To achieve this, we employ a self-supervised reconstruction loss based on Equation 6. Specifically, our loss function calculates the difference between the predicted routing probabilities of the masked grids and their original routing probabilities prior to masking. This approach aligns with the implementation details of Masked Autoencoders (MAE), ensuring consistency and effectiveness in the reconstruction process.

Q1 “most of the design in the proposed network seems not novel and exists in network/method for other domains. I personally think this is not critical as long as the method is working well for this specific domain..”

A1

We appreciate your thoughtful response and the opportunity to address our concerns more comprehensively. As you have rightly pointed out, we have drawn inspiration from the network architectures and self-supervised learning methods in the field of artificial intelligence in designing DeepLayout. However, our direct adaptation of these methodologies to circuit layout representation learning revealed three critical technical challenges:

1） Distinct Graph Structures of Circuit Layouts

An integrated circuit's graph structure, derived from Verilog netlists, differs from traditional graph learning domains. It incorporates gate-level physical properties during technology mapping (e.g., TSMC N3), layout positions, and routing interconnect details—unlike point clouds or social networks, as shown in the table below:

To address this issue, we propose a novel encoder architecture that jointly learns the topological structure and geometric information of the circuit graph structure through the combination of Multi-Scale Graph Attention (MSGA) and Heterogeneous Graph Neural Networks (HGNN). By fully extracting these two types of features, DeepLayout enables comprehensive extraction of topological and spatial features, generating layout representations applicable to routing prediction - a computationally intensive critical phase in circuit design.

2） Limitations of Self-Supervised Learning in Circuit Layouts

Self-supervised learning in computer vision and graph learning relies on inherent labels for restoration tasks, but this approach has limitations in circuit layout learning. First, circuit graphs have low redundancy, making it hard to restore masked node attributes without extra guidance. Second, layout representation learning aims to predict routing-phase quality, but traditional node-masking methods fail to capture routing characteristics.

To overcome these challenges, we propose a self-supervised learning approach tailored for circuit layouts. Our key design points include: 1) introducing a grid-based masking strategy, 2) masking only the geometric information of nodes while retaining edge information as guidance for restoration, and 3) designing two distinct supervised tasks. Notably, Supervised task #2 utilizes the easily computable Routing Probability Algorithm (RPA) feature as a supervisory signal to captures essential aspects of the routing process.

3）Downstream Tasks in Circuit Layout Representation Learning

In graph representation learning, downstream tasks typically involve learning global graph attributes or predicting node classifications, without the need for a specialized decoder. However, downstream tasks in circuit layout learning span multiple levels, from individual nodes to 2D representations.

Q1 It could mention other graph-based learning techniques in EDA beyond CircuitGNN and discuss RL-based methods for backend placement to strengthen the background. if we miss any related papers, please feel free to point out. We will incorporate them in the final version.

A1 We sincerely appreciate your valuable suggestions. In the revised manuscript, we will augment the related work section with a discussion of graph-based learning methods in EDA and reinforcement learning techniques for physical backend design.

Q2 Swap Figure 1 and Figure 2 for better readability. Typo in Page 2, line 93: “Therefor” → “Therefore”. Text and details in Figure 5 are too small to read clearly. Visualizations of congestion predictions in Figure 7 are not clear. Please consider improving contrast and resolution.

A2 We sincerely appreciate your valuable suggestions. We will incorporate these improvements in the final manuscript, including: 1) making the specified revisions to the content; 2) enhancing the clarity of all visualizations.

Q3 "How does DeepLayout perform on larger circuits with millions of components?"

A3 We sincerely appreciate your valuable suggestion. However, preparing larger circuit design data is extremely time-consuming. As a result, we have not been able to complete all the experiments related to large circuit designs at present. We will make every effort to update the experimental data related to large designs in the following days and discuss them with you.

Q4 "What are the computational resource requirements for pretraining DeepLayout?"

A4 The pre-training phase of DeepLayout is performed on an 8 A800 machine, achieving a per-epoch training time of 16 hours. These implementation specifics will be incorporated into the methodology section of our paper.

Q5 "Can DeepLayout generalize to other layout tasks (e.g., DRC prediction, power estimation)?"

A5

Thank you for your valuable suggestions. We have additionally designed post-routing timing prediction task that is directly related to evaluating post-routing layout quality.

Post-Routing Timing Prediction: Timing is directly correlated with the chip's performance. The encoder of DeepLayout is initialized with pre-trained weights, while the decoder employs a specially designed graph neural network. We fine-tune the network using regression loss and perform timing prediction after few-shot fine-tuning. Following common practice in related literature, we report widely adopted metrics including Pearsonr, R², and MAE. The results are presented below.

These experimental results further demonstrate that our proposed pre-training methodology and network architecture can effectively support downstream tasks for characterizing post-routing layout performance. Due to the time-consuming nature of data preparation and network training, we were unable to complete all the experiments related to DRC prediction within the limited number of days. We will make every effort to update the experimental data related to large-scale DRC in the following days and discuss it with you. Concerning the power prediction task: The current public datasets we employ lack power-related labels and critical information such as input vectors or toggle rates. We therefore designate power prediction as a primary downstream task for our future work.

Q6 "Do the authors plan to extend this to full-chip routing prediction?"

A6

We acknowledge the reviewer’s question regarding whether our prediction method operates on full-chip designs. Our approach indeed performs post-routing performance prediction on complete circuit chips. Specifically: 1.Full-Chip Input Representation: Throughout all stages—pre-training, fine-tuning, and testing—DeepLayout processes complete circuit graphs that represent the entire chip design. 2.Post-routing prediction target: In DeepLayout, the labels for all downstream tasks are extracted after the routing process. In other words, the current objective of DeepLayout is to make routing predictions. This distinguishes our work from partial or tile-based prediction approaches, ensuring relevance for real-world chip design optimization.

R1 Q1: "Congestion and wirelength ... strength the paper."

A1 We have additionally designed post-routing timing prediction task that is directly related to evaluating post-routing layout quality. Timing is directly correlated with the chip's performance. The results are presented below.

Area prediction is unnecessary since post-routing layout area remains nearly unchanged from placement, allowing direct calculation. The current public datasets we employ lack power-related labels and critical information such as input vectors or toggle rates. We therefore designate power prediction as a primary downstream task for our future work.

Q2: Line 92, "Therefore" Algorithm 1, line 13, should the index i be involved?

A2： We appreciate your identification of this typo in the manuscript. additionally, in Line 12, "i" should be corrected to "vi," and in Line 13, "vk" should be updated to "vi." These corrections will be reflected in the final version of the paper.

Q3 "A 50% mask ratio ... for this?"

A3: We hypothesize that this difference arises due to both the nature of circuit data and our specialized masking strategy: From the data aspect, Images tend to exhibit a high level of information redundancy, while circuits contain rich information among sub-circuits, which is not easy to restore from the neighbour. From the pre-training method aspect, DeepLayout implements mask nodes within selected grid cells, where each grid size is significantly smaller than the image patches (e.g., 16×16 in MAE). Meanwhile, each grid contains multiple graph nodes, different from the individual node mask style of graph SSL. Thus, the optimal 50% mask ratio emerges as an intermediate value between these two modalities. Due to character limitations, I had to shorten the content. If you have other questions, we can discuss them below.

Q4 "I'm wondering ... networks used." A4 Ablation study of encoder modules Congestion prediction

Post-routing net length prediction

Q5 "Robustness. ... performance?" A5 In response, we adopted a 50% mask ratio and conducted three repeated pre-training runs, followed by evaluations on two downstream tasks. Congestion prediction:

Post-routing wire length prediction

Q6 Will the code ... reproduction? A6 We promise to open-source the DeepLayout code upon paper acceptance.