Runsheng Wang

CircuitNet 3.0: A Multi-Modal Dataset with Task-Oriented Augmentation for AI-Driven Circuit Design

Attention is Not Always Needed: Attention Sink Forges a Native MoE in Attention Layers

MPCache: MPC-Friendly KV Cache Eviction for Efficient Private LLM Inference

DeepLayout: Learning Neural Representations of Circuit Placement Layout

MPCache: MPC-Friendly KV Cache Eviction for Efficient Private LLM Inference

ANALOGXPERT: AUTOMATING ANALOG TOPOLOGY SYNTHESIS BY INCORPORATING CIRCUIT DESIGN EXPERTISE INTO LARGE LANGUAGE MODELS