Chip Placement with Diffusion Models

We thank the reviewer for the insightful feedback. Our response is as follows:

EfficientPlace: Although EfficientPlace uses tree search to address the shortcomings of RL, it still requires significant training on every new circuit to perform well. We present additional experiments on the IBM benchmark below, showing that our method significantly outperforms EfficientPlace in both HPWL and congestion, while requiring a fraction of the time.

Table 1 Congestion and HPWL on IBM

DreamPlace: We highlight that our method outperforms DreamPlace, a very strong baseline, while other macro placement methods fall far short. This could be because DreamPlace relies on gradient descent, which performs a local search, whereas the diffusion model can perform a global search based on the training data. We agree that this additional performance comes at a cost, with our method having a longer runtime as shown in Table 2 below, and requiring several days of training.

Nevertheless, we emphasize that our work explores and develops a novel approach - training diffusion models - for the placement problem, and to our knowledge is the first to apply diffusion to this domain. Developing a method that is competitive with, even marginally outperforming, DreamPlace is still a significant improvement over prior macro placement approaches, and demonstrates that this approach has strong merits. We believe showing this is one of the contributions of our work.

Table 2 Runtimes in minutes

Non-overlap: While it is true that our method does not enforce hard constraints to prevent overlap, we find that in practice this is not an issue. Legality guidance, combined with gradient-based legalization, is effective in ensuring almost no overlaps in our macro placements.

Optimization of other objectives: We presented results on congestion in table 1 above, which shows that our method achieves significantly lower congestion than the baselines. This result is consistent with findings from prior work [1] that finds congestion to be correlated with HPWL.

We agree that downstream metrics such as PPA are important targets for optimization. However, optimizing for PPA is difficult, with many similar works focusing on simple proxy objectives like HPWL. Moreover, the commonly used benchmarks such as ISPD2005 and IBM do not support timing analysis. Because the goal of our work is to explore and develop a novel approach - training a diffusion model - to macro placement, we have therefore chosen to focus our contributions on developing the techniques necessary for such an approach, such as synthetic data generation, rather than simultaneously tackling PPA optimization. Therefore, while PPA optimization is an important end-goal, we leave it as an area for future work.

Answers to Questions:

1. We believe the magnitude in the ChipFormer paper should be 1e5. Table 15 of the MaskPlace paper [2] has the same numbers as those in Table 8 of the ChipFormer paper, but with a scale of 1e5, which is the same as us.

We hope we have been able to address your concerns.

[1] Shi et. al. "Macro Placement by Wire-Mask-Guided Black-Box Optimization." Neurips, 2023.

[2] Lai et. al. "MaskPlace: Fast Chip Placement via Reinforced Visual Representation Learning." Neurips, 2022.

We thank the reviewer for their insightful feedback. Our response is as follows:

Choice of dataset: We choose the IBM dataset for several reasons. First, it contains more circuits - 18, compared to 8 for ISPD2005. Second, the IBM dataset allows for easier comparison with other macro placement methods. The ISPD2005 benchmark contains circuits with a large number of macros (up to 23k), causing prior works to omit these circuits or pick macros to place according to various criteria. The IBM dataset avoids this issue, and allows for consistent evaluation of macro placement methods on all 18 circuits. Nevertheless, we have evaluated our method on the ISPD2005 dataset, using the macro-only setting for easier comparison, with the results shown in Table 1 below. Our method achieves significantly improved performance over the baselines.

Macro-only Evaluations: We agree with this suggestion, and present our results in the tables below.

Table 1 HPWL on ISPD2005 benchmark

Table 2 HPWL on IBM benchmark

Time overhead: We present the runtimes for our method and baselines in the table below. Our method is significantly faster than other macro placement methods, taking on average 4 and 20 minutes on the IBM and ISPD benchmarks respectively, compared to RL or BBO methods that take 10 times longer. We note however that we are slower than Dreamplace, and further optimization of our code and diffusion sampling is an interesting area of future work.

Table 3 Runtimes in minutes

To clarify, we used Dreamplace 4.1, and will correct the citation to reflect this.

Answers to questions:

1. Our motivation for choosing IBM is detailed above. We have also performed additional experiments on the ISPD05 benchmark, with results shown in Table 1 above.

2. Yes, Table 2 in the ChipFormer paper reports macro-only HPWL, whereas Table 5 in our paper reports mixed-size HPWL.

3. x is a (V x 2) array, where V is the number of objects in the netlist, containing the 2D positions of all objects, which includes macros and standard cell clusters.

We hope we have been able to address your concerns.

We thank the reviewer for their helpful feedback. Our response is as follows:

Additional benchmarks: We have included experiments on the ISPD2005 benchmark, which we show in the table below. To facilitate comparison with baselines, we follow the suggestion of reviewer m7a3 and present HPWL and congestion in the macro-only setting. These results show that our method significantly outperforms baselines on this benchmark as well.

Table 1 Congestion and HPWL of macro placements on ISPD2005

We hope we have been able to address your concerns.

Thank you for your insightful feedback and suggestions. We hope the following can address your concerns.

PPA evaluation: We agree that PPA evaluation and optimization is important. As a step towards analyzing and optimizing downstream objectives, we also evaluated congestion of our macro placements, with the results in Table 1 below showing that our method significantly outperforms the baselines not just in HPWL, but in congestion.

However, optimizing for PPA is difficult, with many similar works focusing on simple proxy objectives like HPWL. Moreover, the commonly used benchmarks such as ISPD2005 and IBM do not support timing analysis. Because the goal of our work is to explore and develop a novel approach - training a diffusion model - to macro placement, we have therefore chosen to focus our contributions on developing the techniques necessary for such an approach, such as synthetic data generation, rather than simultaneously tackling PPA optimization. We believe that despite its shortcomings, HPWL is a reasonable optimization objective, particularly as a first step when exploring a new approach.

Therefore, while PPA optimization is an important end-goal, we leave it as a direction for future work.

Table 1 Congestion on IBM macro placements.

Validity of synthetic data: We trained different-sized models on a dataset generated using Flora’s algorithm and found that models trained on their dataset show much poorer legality than ours when evaluated on the clustered IBM circuits. This indicates that the Flora dataset generalizes poorly, in contrast to ours. The results below are after 1M training steps.

Table 2 Performance of Large and Medium models trained on different datasets.

Training RL with synthetic data: This is a good point, and we believe this to be an interesting experiment to perform in the future.

Clustering standard cells: We performed mixed-size placement on the IBM benchmark using clustered standard cells (our approach), and the suggested approach (also commonly used in literature) of first placing macros only. The results below show that using clustered standard cells performs better, likely because the macro positions can be informed by connectivity and space needed for standard cells.

Table 3 Mixed-size placement performance with and without standard cell clusters.

Recent papers: We have conducted additional experiments comparing with EfficientPlace[1] in the macro-only setting, which we show below. Although EfficientPlace uses tree search to address the shortcomings of RL, our method still produces higher-quality samples in HPWL, while requiring a fraction of the sampling time.

Table 4 Comparison of various methods, including EfficientPlace, on the IBM benchmark.

Answers to questions:

1. We used the official implementations and trained on the test (ie. IBM benchmark) circuits.
2. We post-processed the macro placements with our own gradient-based legalizer. Combined with legality guidance, this method is effective in ensuring almost no overlaps.
3. As mentioned in section 5.1.4, we do use a diverse range of scales to generate our dataset, sampling the scale from a log-uniform distribution, with a range of (0.05, 1.6) and (0.025, 0.8) for the v1 and v2 datasets respectively.

We thank the reviewer for the helpful comments on the writing and clarity of our paper, and will be sure to make the necessary changes. We hope we have been able to address your concerns.

[1] Reinforcement Learning within Tree Search for Fast Macro Placement. ICML'24.