Rui Zhang

Code Driven Planning with Domain-Adaptive Selector

LocalV: Exploiting Information Locality for IP-level Verilog Generation

Circuit HMM: A Deterministic Hidden Markov Model for Automated Sequential Circuit Design

GOOD: Decoding-Time Black-Box LLM Alignment

QiMeng-CodeV-R1: Reasoning-Enhanced Verilog Generation

QiMeng-NeuComBack: Self-Evolving Translation from IR to Assembly Code

QiMeng-SALV: Signal-Aware Learning for Verilog Code Generation

QiMeng-MuPa: Mutual-Supervised Learning for Sequential-to-Parallel Code Translation

GOOD: Decoding-Time Black-Box LLM Alignment

GOOD: Decoding-Time Black-Box LLM Alignment

Adversarial Contrastive Decoding: Aligning Large Language Models via Exploiting Their Safety and Harm