Zidong Du

Code Driven Planning with Domain-Adaptive Selector

LocalV: Exploiting Information Locality for IP-level Verilog Generation

Circuit HMM: A Deterministic Hidden Markov Model for Automated Sequential Circuit Design

QiMeng-CodeV-R1: Reasoning-Enhanced Verilog Generation

QiMeng-SALV: Signal-Aware Learning for Verilog Code Generation

Adversarial Contrastive Decoding: Aligning Large Language Models via Exploiting Their Safety and Harm